The present invention relates to improvements in MOS integrated circuits each having at least one charging transistor and at least one discharging transistor.
Recently, advances in circuit integrating technology have resulted in increasingly miniaturized MOS transistors. The advancement of the microfabrication technology, however, creates problems, e.g., increase of impact ionization current and injection of hot electrons into the gate oxide film.
It will be explained how impact ionization occurs, and how hot electrons are generated. When a MOS transistor operates in the pentode operating region (VD.gtoreq.VG-VTH, where VD is the drain voltage of the transistor, VG the gate voltage, and VTH the threshold voltage), its channel fails to reach the drain. Under this condition, a depletion layer is formed between the drain and channel of the transistor. In the case of a miniaturized transistor, the surface electric field at the edge of the drain is extremely intense, and the electrons moving through the channel gain large amounts of energy and become hot electrons. The hot electrons break through a potential barrier of Si--SiO.sub.2 and enter a gate oxide film. Some of the electrons form a gate current. Remaining electrons are trapped in the gate oxide film. The longer the MOS integrated circuit is used the more electrons are accumulated in the gate oxide film. The threshold voltage of the MOS transistor varies, and the drive current is reduced. In the worst case, the integrated circuit fails to function correctly.
In the depletion layer formed between the channel and the drain, the hot electrons hit silicon crystals, generating electron-hole pairs. Hence, carriers are multiplied. The resultant holes move through a semiconductor substrate, providing an impact ionization current. The substrate current greatly increases, bringing about undesired phenomena, i.e., a change in the substrate voltage from its design value, and forward biasing of the PN junction.
When the MOS transistor operates in a triode operating region (VG&lt;VG-VTH), the depletion layer is not formed between the channel and the drain, and the surface electric field is uniformly distributed. The generation of hot electrons and the increase of the impact ionization current can be restricted.
As mentioned above, when hot electrons and/or impact current is generated, the substrate current increases, the threshold voltage varies, and the drive ability of the transistor is reduced.
A transistor with an LDD (Lightly Doped Drain-Source) structure, has been proposed in which there is no localization of the electric field, and generation of hot electrons and impact ionization current is minimized. In this transistor, N type low doped impurity diffusion layers are formed on the sides of N type highly doped impurity diffusion layers serving as the sources or drains. The LDD transistor is disclosed in Seki, Ogawa, et al., Design and Characteristics of the Lightly Dooed Drain-Source (LDD) Insulated Gate Field-Effect Transistor, IEEE ED-27, 1980, pp 1359 to 1367, FIG. 1(a).
In the LDD transistor, an N.sup.- impurity diffusion layer widens the depletion layer in the N region, weakening or attenuating the electric field at the drain end where the field is particularly intense. In this way, hot electron generation is reduced.
The LDD transistor has N.sup.- layers with high resistivity. The LDD transistor can be regarded as having a relatively large equivalent resistor connected between the drain and the source. The equivalent resistor reduces the current flowing between the source and drain by approximately 20%. To compensate for the reduction of current, the channel width of the transistor must be 20 to 30% greater than that of transistors having no N.sup.- layer.
For this reason, the conventional LDD transistor causes many problems. The chip area occupied by the transistors is large, and the chip size is large. Further, increase of the load capacity deteriorates the switching speed of the switching transistors, and power dissipation is increased.